Impedance
Controlled Impedance Design
Like sizing water pipes just right so nothing leaks or echoes, we shape the copper wires on a board so fast signals travel cleanly without errors.
Signal traces that hit their target impedance across process variation, proven by TDR coupons.
- Tolerance
- ±5% typical, ±10% relaxed
- Solver
- 2D field solver
- Targets
- 50/90/100 ohm and custom
- Verification
- TDR impedance coupon
Controlled impedance keeps high-speed signals — DDR, PCIe, USB, Ethernet, LVDS — reflection-free by holding trace geometry and dielectric to a defined characteristic impedance. We build the stackup with a 2D field solver, not rule-of-thumb tables.
Field-solver stackups
We model each signal layer against its reference planes, accounting for:
- Dielectric constant (Dk) and loss (Df) at the operating frequency, per the actual laminate datasheet.
- Copper weight and etch-back trapezoid, which shifts real impedance from the drawn width.
- Solder mask and prepreg resin content, which alter the effective Dk near the surface.
Single-ended and differential
| Target | Common application |
|---|---|
| 50 Ω single-ended | RF, general high-speed |
| 90 Ω differential | USB 2.0/3.x |
| 100 Ω differential | Ethernet, LVDS, PCIe |
| 85 Ω differential | SATA, some SerDes |
We tune line width, spacing, and layer height to hit target within ±5%, and account for coupling in tightly routed differential pairs.
Verification coupons
Every controlled-impedance job carries a TDR impedance coupon on the panel, built from the same materials on the same layers. The fabricator measures it with a time-domain reflectometer and reports actual impedance, giving you traceable proof rather than a modeled assumption.
The deliverable is a solver-backed stackup drawing, per-layer trace-width tables, and coupon definitions ready for CAM panelization.
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